1. Field of the Invention
The present invention relates generally to SERDES (serializer/deserializer) transceivers, and more particularly, to a digital phase locked loop within a SERDES transceiver.
2. Discussion of the Related Art
FIG. 1 shows a conventional SERDES (serializer/deserializer) transceiver 100 coupled between a high speed data communication media 102 and a low speed data processor 104. The high speed data communication media 102 is for sending serial data bits to the low speed data processor 104 at relatively high speeds. The low speed data processor 104 then receives and processes such data at a lower speed. For example, the high speed data communication media 102 may be a network of optical fibre channels operating at the relatively high speed of 1.25 GHz (giga-Hertz) for instance, and the low speed data processor 104 may be a computer system for processing such data received from the high speed data communication media 102. Such high speed data communication media 102 and such low speed data processor 104 are known to one of ordinary skill in the art of SERDES transceivers.
Within the SERDES transceiver 100, a clock data recovery deserializer 106 receives a high speed serial data input (SDIN) from the high speed data communication media 102 and recovers an embedded serial clock signal (SCLK) from the high speed serial data input (SDIN). The clock data recovery deserializer 106 uses a plurality of given clock signals (HCLK1−n) generated by a clock synthesizer phase locked loop 108 to recover the serial clock signal (SCLK). The clock synthesizer phase locked loop 108 generates each of the plurality of given clock signals (HCLK1−n) from a reference clock signal (REFCLK) provided by the low speed data processor 104. Each of the plurality of given clock signals (HCLK1−n) has a substantially same frequency that is an expected frequency of the recovered serial clock signal (SCLK) of the high speed serial data input (SDIN) but has different phases from each other.
In addition, the clock data recovery deserializer 106 uses the recovered serial clock signal (SCLK) to sample the high speed serial data input (SDIN) for generating a v-bits wide recovered parallel data output (RPDO) for every cycle of a recovered parallel clock signal (RPCLK). The recovered parallel clock signal is generated for every v-cycles of the recovered serial clock signal (SCLK). The recovered parallel data output (RPDO) and the recovered parallel clock signal (RPCLK) are sent from the clock data recovery deserializer 106 to the low speed data processor 104 for further processing of such data at relatively slower speeds by the low speed data processor 104.
The reference clock signal (REFCLK) from the low speed data processor 104 and the recovered parallel clock signal (RPCLK) have a substantially same frequency since the ratio of the frequency of the recovered serial clock signal (SCLK) to the frequency of the reference clock signal (REFCLK) or to the frequency of the recovered parallel clock signal (RPCLK) is substantially same. The ratio of the frequency of the recovered serial clock signal (SCLK) to the frequency of the reference clock signal (REFCLK) or to the frequency of the recovered parallel clock signal (RPCLK) is “v” with the recovered parallel data output (RPDO) being “v”-bits wide. However, the phase of the reference clock signal (REFCLK) may differ from the phase of the recovered parallel clock signal (RPCLK) since the recovered parallel clock signal (RPCLK) is synchronized with the output of the v-bits wide recovered parallel data output (RPDO).
On the transmitting side, a transmit serializer 110 receives a v-bits wide transmitted parallel data input (TPDIN) and the reference clock signal (REFCLK) from the low speed data processor 104. The reference clock signal (REFCLK) is synchronized with the v-bits wide transmitted parallel data input (TPDIN). The transmit serializer 110 uses the higher frequency of a given clock signal (HCLK) from the clock synthesizer phase locked loop 108 to convert the v-bits wide transmitted parallel data input (TPDIN) to a high speed serial data output (SDOUT) to be transmitted over the high speed data communication media 102. The high speed serial data output (SDOUT) is transmitted as serial data bits at the higher speed of the given clock signal (HCLK) which has a substantially same frequency as the recovered serial clock signal (SCLK).
Such a SERDES transceiver 100 and such operations and components 106, 108, and 110 of the SERDES transceiver 100 are known to one of ordinary skill in the art of high speed data communications.
FIG. 2 shows the components of the clock data recovery deserializer 106 of FIG. 1. A clock recovery phase locked loop 112 inputs the high speed serial data input (SDIN) and generates the recovered serial clock signal (SCLK). The recovered serial clock signal (SCLK) is input by a clock divider 114 and a serial-to-parallel shift register 116. The serial-to-parallel shift register 116 shifts in a bit of the high speed serial data input (SDIN) every cycle of the recovered serial clock signal (SCLK).
The clock divider generates the recovered parallel clock signal (RPCLK) having a cycle for every “v” cycles of the recovered serial clock signal (SCLK). The recovered parallel clock signal (RPCLK) is input by the serial-to-parallel shift register 116 to generate the recovered parallel data output (RPDO) comprised of v-bits of the high speed serial data input (SDIN) at a predetermined transition of every cycle of the recovered parallel clock signal (RPCLK). A SYNC detect logic 118 asserts a VRS (divider ReSet) signal (i.e., a parallel clock enabling signal) for determining the timing of such a predetermined transition of every cycle of the recovered parallel clock signal (RPCLK) such that the high speed serial data input (SDIN) is properly partitioned to generate each of the v-bits of the recovered parallel data output (RPDO). The SYNC detect logic 118 inputs the high speed serial data input (SDIN) and asserts the VRS signal at the occurrence of a predetermined bit pattern within the high speed serial data input (SDIN).
Such a clock data recovery deserializer 106 and such operations and components 112, 114, 116, and 118 of the clock data recovery deserializer 106 are known to one of ordinary skill in the art of SERDES transceivers.
FIG. 3 shows a timing diagram of an example high speed serial data input (SDIN) 101, an example recovered serial clock signal (SCLK) 103, and examples of possible recovered parallel clock signals (RPCLK). The cross-hatched region of the high speed serial data input (SDIN) 101 represents a time period when the high speed serial data input (SDIN) 101 may make a transition, and the time period between the cross-hatched regions represents a time period when the high speed serial data input (SDIN) 101 has a stable data bit, including a first data bit 105, a second data bit 107, a third data bit 109, a fourth data bit 111, and a fifth data bit 113. The example recovered serial clock signal (SCLK) 103 represents a desired recovered serial clock signal (SCLK) with each low-to-high transition of the recovered serial clock signal (SCLK) 103 occurring substantially at the middle of each stable data bit of the high speed serial data input (SDIN) 101 (as illustrated by dashed line 115 for example in FIG. 3).
Referring to FIGS. 2 and 3, assume that the recovered parallel data output (RPDO) is comprised of three-bits, and that the proper partitioning of three data bits in FIG. 3 is to include the first, second, and third data bits 105, 107, and 109. For such three data bits, a first recovered parallel clock signal (RPCLK1) 117, a second recovered parallel clock signal (RPCLK2) 119, and a third recovered parallel clock signal (RPCLK3) 121 are possible. If the three data bits after the low-to-high transition of the recovered parallel clock signal (RPCLK) is to comprise the three-bits of the recovered parallel data output (RPDO), then for a cycle 123 of the first recovered parallel clock signal (RPCLK1) 117, the recovered parallel data output (RPDO) is comprised of the first, second, and third data bits 105, 107, and 109. On the other hand, for a cycle 125 of the second recovered parallel clock signal (RPCLK2) 119, the recovered parallel data output (RPDO) is comprised of the second, third, and fourth data bits 107, 109, and 111. For a cycle 127 of the third recovered parallel clock signal (RPCLK3) 121, the recovered parallel data output (RPDO) is comprised of the third, fourth, and fifth data bits 109, 111, and 113.
Thus, if the proper partitioning of the high speed serial data input (SDIN) 101 is to include the three-bits of the first, second, and third data bits 105, 107, and 109, then the first recovered parallel clock signal (RPCLK1) 117 is the desired one of the possible first, second, and third recovered parallel clock signals (RPCLK1, RPCLK2, and RPCLK3) 117, 119, and 121. The VRS signal from the SYNC detect logic 118 determines the time of occurrence of the low-to-high transition of the recovered parallel clock signal (RPCLK) to ensure that the first recovered parallel clock signal (RPCLK1) 117 (instead of the second or third possible recovered parallel clock signals RPCLK2 and RPCLK3) is the recovered parallel clock signal (RPCLK) sent to the serial-to-parallel shift register 116.
The SYNC detect logic 118 asserts the VRS signal at the occurrence of a predetermined synchronization bit pattern within the high speed serial data input (SDIN). One of the drawbacks of conventional SERDES transceivers is their inability to recognize synchronization bit patterns of different communications protocols. In prior art SERDES transceivers, the SYNC detect logic is constructed to recognize only a single synchronization bit pattern. Different communications protocols, however, have different synchronization bit patterns. A SERDES transceiver having such prior art SYNC detect logic 118 cannot receive and process high speed serial data input (SDIN) having different synchronization bit patterns.
Another drawback of conventional SERDES transceivers is their inability to minimize bit error rates for different communications protocols. FIG. 4 shows the prior art components of the clock recovery phase locked loop 112 of FIG. 2 including a phase detector 120, a digital filter 122, and a phase selector 124 for generating the recovered serial clock signal (SCLK) from the high speed serial data input (SDIN). The phase selector 124 inputs the given clock signals (HCLK1−n) from the clock synthesizer phase locked loop 108 of FIG. 1 and selects one of such given clock signals as the recovered serial clock signal (SCLK). The phase selector 124 selects one of the given clock signals (HCLK1−n) as the recovered serial clock signal (SCLK) depending on the values of a FWD signal and a BWD signal generated by the digital filter 122.
FIG. 5 shows a timing diagram of an example high speed serial data input (SDIN) 130 and an example recovered serial clock signal (SCLK) 134. A complementary recovered serial clock signal (ACLK) 132 is the recovered serial clock signal (SCLK) 134 that is 180° phase-shifted. The cross-hatched region of the high speed serial data input (SDIN) 130 represents a transition time period when the high speed serial data input (SDIN) 130 may make a transition, and the time period between the cross-hatched regions represents a stable data time period when the high speed serial data input (SDIN) 130 has a stable data bit.
For the desired recovered serial clock signal (SCLK) 134 and the desired complementary recovered serial clock signal (ACLK) 132, each low-to-high transition of the complementary recovered serial clock signal (ACLK) 132 occurs substantially at the middle of the cross-hatched region representing the transition time period when the high speed serial data input (SDIN) 130 makes a transition (illustrated by dashed line 133 in FIG. 5). Conversely, each low-to-high transition of the recovered serial clock signal (SCLK) 134 occurs substantially at the middle of the region representing the stable data time period when the high speed serial data input (SDIN) 130 has a stable data bit (illustrated by dashed line 135 in FIG. 5).
FIG. 5 also shows example given clock signals (HCLK1−n) from the clock synthesizer phase locked loop 108 of FIG. 1 including a first given clock signal HCLK1 136, a second given clock signal HCLK2 138, a third given clock signal HCLK3 140, a fourth given clock signal HCLK4 142, a fifth given clock signal HCLK5 144, a sixth given clock signal HCLK6 146, a seventh given clock signal HCLK7 148, and an eighth given clock signal HCLK8 150. Each of the given clock signals (HCLK1−n) are arranged in a predetermined phase order such that any two adjacent given clock signals (HCLKj and HCLKj+1) have a substantially same predetermined phase difference. In addition, the first given clock signal HCLK1 136 and the eighth given clock signal HCLK8 150 which is the last of the given clock signals (HCLK1−n) in the phase order in the example of FIG. 5 has that substantially same predetermined phase difference. Thus, the example given clock signals (HCLK1−n) of FIG. 5 have a successive phase difference of 45°.
If the FWD signal is asserted by the digital filter 122, then the phase selector 124 selects another clock signal (HCLKj+1) of the given clock signals that immediately leads a priorly selected one (HCLKj) of the given clock signals as the recovered serial clock signal (SCLK). If the BWD signal is asserted by the digital filter 122, then the phase selector 124 selects another clock signal (HCLKj−1) of the given clock signals that immediately lags the priorly selected one (HCLKj) of the given clock signals as the recovered serial clock signal (SCLK). If neither the FWD signal nor the BWD signal is asserted, then the phase selector 124 selects the priorly selected one (HCLKj) of the given clock signals to remain as the recovered serial clock signal (SCLK). In the example of FIG. 5, eventually, the seventh given clock signal HCLK7 is selected as the desired recovered serial clock signal (SCLK) 134, and the third given clock signal HCLK3 is selected as the desired complementary recovered serial clock signal (ACLK) 132.
The phase detector 120 inputs the high speed serial data input (SDIN) and compares the phase of the high speed serial data input (SDIN) to the phase of the recovered serial clock signal (SCLK) from the phase selector 124. The phase detector 120 generates a DN signal pulse if the high speed serial data input (SDIN) leads the recovered serial clock signal (SCLK) and generates an UP signal pulse if the high speed serial data input (SDIN) lags the recovered serial clock signal (SCLK). The digital filter 122 counts the number of such UP signal pulses to assert the FWD signal after generation of at least a predetermined number of UP signal pulses or to assert the BWD signal after generation of at least a predetermined number of DN signal pulses. Such a clock recovery phase locked loop 112 which is a digital phase locked loop and such operations and components 120, 122, and 124 of the clock recovery phase locked loop 112 are known to one of ordinary skill in the art of SERDES transceivers.
Assertion of the FWD signal or the BWD signal by the digital filter 122 after counting such UP signal pulses or DN signal pulses to at least the predetermined number ensures that the FWD signal or the BWD signal is asserted only when the high speed serial data input (SDIN) significantly leads or lags the recovered serial clock signal (SCLK). In this manner, the FWD signal or the BWD signal is not asserted when the high speed serial data input (SDIN) leads or lags the recovered serial clock signal (SCLK) only because of temporary glitches or noise.
In addition, the digital filter 122 determines an average (i.e., a trend) of whether the high speed serial data input (SDIN) leads or lags the recovered serial clock signal (SCLK) by counting such UP signal pulses or DN signal pulses to at least the predetermined number. When the phase detector 120 generates the UP signal pulses and the DN signal pulses by comparing the transitions of the high speed serial data input (SDIN) to the transitions of the recovered serial clock signal (SCLK), the predetermined number of the UP signal pulses and the DN signal pulses that the digital filter 122 counts up to for asserting the FWD signal or the BWD signal determines the bit error rate of the SERDES transceiver 100, as known to one of ordinary skill in the art of SERDES transceivers.
In the prior art digital filter 122, this predetermined number of the UP signal pulses and the DN signal pulses that the digital filter 122 counts up to for asserting the FWD signal or the BWD signal is fixed. However, each communications protocol has a respective optimum range of the predetermined number of UP signal pulses and the DN signal pulses that the digital filter counts up to for asserting the FWD signal or the BWD signal such that the bit error rate is minimized for each communications protocol. When the predetermined number of UP signal pulses and the DN signal pulses that the digital filter 122 counts up to for asserting the FWD signal or the BWD signal is fixed for a predetermined communications protocol, the SERDES transceiver having such a prior art digital filter 122 cannot be used for receiving and processing high speed serial data input (SDIN) of another communications protocol with minimized bit error rate for that other communications protocol.
In the prior art, another SERDES transceiver having a digital filter that counts to a different predetermined number of the UP signal pulses and the DN signal pulses for asserting the FWD signal or the BWD signal needs to be manufactured to minimize the bit error rate of another communications protocol. However, such manufacture of various SERDES transceiver to accommodate different communications protocols may be costly. Nevertheless, the high speed serial data input (SDIN) may be communicated according to multiple communications protocols.
A third drawback of conventional SERDES transceivers is their inability to provide additional phases of the recovered clock signal (SCLK) without minimized consumption of increased chip area and power since each additional phase interpolator consumes additional chip area and power.